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x25f064/032/016/008 1 x25f064/032/016/008 serialflash? and block lock? protection are trademarks of xicor, inc. serialflash? memory with block lock tm protection features ? 1mhz clock rate ? spi serial interface ? 64k/32k/16k/8k bits 32 byte small sector program mode ? low power cmos <1 m a standby current <5ma active current ? 1.8v C 3.6v and 5v univolt read and program power supply ? block lock protection protect 1/4, 1/2, or all of e 2 prom array ? built-in inadvertent program protection power-up/power-down protection circuitry program enable latch program protect pin ? self-timed program cycle 5ms program cycle time (typical) ? high reliability endurance: 100,000 cycles per byte data retention: 100 years esd protection: 2000v on all pins ? 8-lead pdlp package ? 8-lead 150 mil soic packages ? 32k, 16k, 8k available in 14-lead tssop, 64k available in 20-lead tssop description the x25f064/032/016/008 family are 8/16/32/64k-bit cmos serialflash memory, internally organized x 8. they feature a univolt program and read voltage, serial peripheral interface (spi), and software protocol allowing operation on a simple three-wire bus. the bus signals are a clock input (sck), plus separate data in (si) and data out (so) lines. access to the device is controlled through a chip select ( cs ) input, allowing any number of devices to share the same bus. the x25f064/032/016/008 also features two additional inputs that provide the end user with added flexibility. by asserting the hold input, the x25f064/032/016/008 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. the pp input can be used as a hardwire input to the x25f064/032/016/008 disabling all program attempts to the status register, thus providing a mechanism for limiting end user capa- bility of altering 0, 1/4, 1/2, or all of the memory. the x25f064/032/016/008 utilizes xicors proprietary flash cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. functional diagram ? xicor, inc. 1995, 1996 patents pending characteristics subject to change without notice 6685-2.9 6/25/96 t1/c0/d0 ns 6685 ill f01.4 command decode and control logic x decode logic memory array si so cs hold status register programming control logic pp high voltage control sector decode logic 32 8 data register sck
2 x25f064/032/016/008 hold ( hold hold hold hold hold ) hold is used in conjunction with the cs pin to select the device. once the part is selected and a serial sequence is underway, hold may be used to pause the serial communication with the controller without resetting the serial sequence. to pause, hold must be brought low while sck is low. to resume communication, hold is brought high, again while sck is low. if the pause feature is not used, hold should be held high at all times. pin names symbol description cs chip select input so serial output si serial input sck serial clock input pp program protect input v ss ground v cc supply voltage hold hold input nc no connect 6685 pgm t01.1 pin descriptions serial output (so) so is a push-pull serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. serial input (si) si is the serial data input pin. all opcodes, byte addresses, and data to be written to the memory are input on this pin. data is latched by the rising edge of the serial clock. serial clock (sck) the serial clock controls the serial bus timing for data input and output. opcodes, addresses, or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin change after the falling edge of the clock input. chip select ( cs cs cs cs cs ) when cs is high, the x25f064/032/016/008 is deselected and the so output pin is at high impedance and unless an internal program operation is underway the x25f064/032/016/008 will be in the standby power mode. cs low enables the x25f064/032/016/008, placing it in the active power mode. it should be noted that after power-up, a high to low transition on cs is required prior to the start of any operation. program protect ( pp pp pp pp pp ) when pp is low and the nonvolatile bit ppen is 1, nonvolatile programming of the x25f064/032/016/008 status register is disabled, but the part otherwise func- tions normally. when pp is held high, all functions, including nonvolatile programming operate normally. pp going low while cs is still low will interrupt programming of the x25f064/032/016/008 status regis- ter. if the internal program cycle has already been initiated, pp going low will have no effect on program- ming. the pp pin function is blocked when the ppen bit in the status register is 0. this allows the user to install the x25f064/032/016/008 into a system with pp pin grounded and still be able to program the status register. the pp pin functions will be enabled when the ppen bit is set 0. pin configuration 6685 ill f02.4 cs so pp v ss 1 2 3 4 8 7 6 5 v cc hold sck si 8-lead dip/soic 14-lead tssop 20-lead tssop cs so nc nc nc pp v ss 1 2 3 4 5 6 7 v cc hold nc nc nc sck si 14 13 12 11 10 9 8 nc cs nc so nc nc pp v ss nc nc 1 2 3 4 5 6 7 8 9 10 nc v cc nc hold nc nc sck si nc nc 20 19 18 17 16 15 14 13 12 11 x25f064/ 032/016/ 008 X25F032/ 016/008 x25f064
x25f064/032/016/008 3 formatted as follows: ppen, bl0, and bl1 are set by the prsr instruction. pel and pip are read-only and automatically set by other operations. the programming-in-process (pip) bit indicates whether the x25f064/032/016/008 device is busy with a program operation. when set to a 1 programming is in progress, when set to a 0 no programming is in progress. during programming, all other bits are set to 1. the program enable latch (pel) bit indicates the status of the program enable latch. when set to a 1 the latch is set; when set to a 0 the latch is reset. the block lock (bl0 and bl1) bits are nonvolatile and allow the user to select one of four levels of protection. the x25f064/032/016/008 device array is divided into four equal segments. one, two, or all four of the seg- ments may be locked. that is, the user may read the segments, but will be unable to alter (program) data within the selected segments. the partitioning is con- trolled as illustrated below. status register bits array addresses bl1 bl0 locked 0 0 none 0 1 upper fourth 1 0 upper half 1 1 all 6685 pgm t03.1 program-protect enable the program-protect-enable bit (ppen) in the x25f064/032/016/008 status register acts as an enable bit for the pp pin. principles of operation the x25f064/032/016/008 family are serialflash memory designed to interface directly with the synchro- nous serial peripheral interface (spi) of many popular microcontroller families. the x25f064/032/016/008 family contains an 8-bit instruction register. it is accessed via the si input, with data being clocked in on the rising sck. cs must be low and the hold and pp inputs must be high during the entire operation. the pp input is dont care if ppen is set 0. table 1 contains a list of the instructions and their operation codes. all instructions, addresses and data are transferred msb first. data input is sampled on the first rising edge of sck after cs goes low. sck is static, allowing the user to stop the clock and then resume operations. if the clock line is shared with other peripheral devices on the spi bus, the user can assert the hold input to place the x25f064/ 032/016/008 into a pause condition. after releasing hold , the x25f064/032/016/008 device will resume operation from the point when hold was first asserted. program enable latch the x25f064/032/016/008 device contains a program enable latch. this latch must be set before a program operation will be completed internally. the pren instruction will set the latch and the prdi instruction will reset the latch. this latch is automatically reset on power-up and after the completion of a sector program or status register write cycle. status register the rdsr instruction provides access to the status register. the status register may be read at any time, even during a program cycle. the status register is 7 654 3 2 1 0 ppen x x x bl1 bl0 pel pip 6685 pgm t02.2 table 1. instruction set instruction name instruction format* operation pren 0000 0110 set the program enable latch (enable program operations) prdi 0000 0100 reset the program enable latch (disable program operations) rdsr 0000 0101 read status register prsr 0000 0001 program status register read 0000 0011 read from memory array beginning at selected address program 0000 0010 program memory array beginning at selected address (32 bytes) 6685 pgm t04.2 *instructions are shown msb in leftmost position. instructions are transferred msb first.
4 x25f064/032/016/008 locked unlocked status ppen pp pp pp pp pp pel blocks blocks register 0 x 0 locked locked locked 0 x 1 locked programmable programmable 1 low 0 locked locked locked 1 low 1 locked programmable locked x high 0 locked locked locked x high 1 locked programmable programmable 6685 pgm t05.2 the program protect ( pp ) pin and the nonvolatile program protect enable (ppen) bit in the status reg- ister control the programmable hardware write protect feature. hardware program protection is enabled when pp pin is low, and the ppen bit is 1. hardware program protection is disabled when either the pp pin is high or the ppen bit is 0. when the chip is hardware program protected, nonvolatile programming of the sta- tus register in disabled, including the block lock bits and the ppen bit itself, as well as the block lock sections in the memory array. only the sections of the memory array that are not block locked can be pro- grammed. note: since the ppen bit is program protected, it cannot be changed back to a 0, as long as the pp pin is held low. clock and data timing data input on the si line is latched on the rising edge of sck. data is output on the so line by the falling edge of sck. read sequence when reading from the serialflash memory array, cs is first pulled low to select the device. the 8-bit read instruction is transmitted to the x25f064/032/016/008 device, followed by the 16-bit address. after the read opcode and address are sent, the data stored in the memory at the selected address is shifted out on the so line. the data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. the address is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached the address counter rolls over to address $0000, allowing the read cycle to be continued indefinitely. the read operation is terminated by taking cs high. refer to the read serialflash memory array operation sequence illustrated in figure 1. to read the status register, the cs line is first pulled low to select the device followed by the 8-bit instruc- tion. after the read status register opcode is sent, the contents of the status register are shifted out on the so line. the read status register sequence is illustrated in figure 2. programming sequence prior to any attempt to program the x25f064/032/016/ 008 device, the program enable latch must first be set by issuing the pren instruction (see figure 3). cs is first taken low, then the pren instruction is clocked into the x25f064/032/016/008 device. after all eight bits of the instruction are transmitted, cs must then be taken high. if the user continues the programming operation without taking cs high after issuing the pren instruc- tion, the programming operation will be ignored. to program the serialflash memory array, the user issues the program instruction, followed by the ad- dress of the first location in the sector and then the data to be programmed. the data is programmed in a 256- clock operation. cs must go low and remain low for the duration of the operation. the 32 bytes must reside in the same sector and cannot cross sector boundaries. if the address counter reaches the end of the sector and the clock continues, or if fewer than 32 bytes are clocked in, the contents of the sector cannot be guaranteed. for the program operation to be completed, cs can only be brought high after bit 0 of data byte 32 is clocked in. if it is brought high at any other time the program operation will not be completed. refer to figure 4 below for a detailed illustration of the programming sequence and time frames in which cs going high is valid. to program the status register, the prsr instruction is followed by the data to be programmed. data bits 0, 1, 4, 5 and 6 must be 0. this sequence is shown in figure 5. while the program cycle is in progress, following a status register or memory write sequence, the status register may be read to check the pip bit. during this time the pip bit will be high. hold operation the hold input should be high (at v ih ) under normal operation. if a data transfer is to be interrupted hold can be pulled low to suspend the transfer until it can be resumed. the only restriction is that the sck input must be low when hold is first pulled low and sck must also be low when hold is released. the hold input may be tied high either directly to v cc or tied to v cc through a resistor.
x25f064/032/016/008 5 figure 1. read serialflash memory array operation sequence operational notes the device powers-up in the following state: ? the device is in the low power standby state. ? a high to low transition on cs is required to enter an active state and receive an instruction. ? so pin is high impedance. ? the program enable latch is reset. data protection the following circuitry has been included to prevent inadvertent programming: ? the program enable latch is reset upon power-up. ? a program enable instruction must be issued to set the program enable latch. ? cs must come high at the proper clock count in order to start a program cycle. figure 2. read status register operation sequence 012345678910 2021222324252627282930 76543210 data out cs sck si so msb high impedance instruction 16 bit address 151413 3210 6685 ill f03 01234567891011121314 76543210 data out cs sck si so msb high impedance instruction 6685 ill f04
6 x25f064/032/016/008 figure 3. program enable latch sequence 01234567 6685 ill f05.1 cs si sck high impedance so instruction
x25f064/032/016/008 7 figure 5. program status register operation sequence figure 4. programming sequence 32 33 34 35 36 37 38 39 sck si cs 012345678910 sck si instruction 16 bit address data byte 1 76543210 cs 40 41 42 43 44 45 46 47 data byte 2 76543210 data byte 3 76543210 data byte 32 151413 3210 20 21 22 23 24 25 26 27 28 29 30 31 6543210 6685 ill f07.1 0123456789 cs sck si so high impedance instruction data byte 76543210 10 11 12 13 14 15 6685 ill f08
8 x25f064/032/016/008 *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings* temperature under bias .................. C65 c to +135 c storage temperature ....................... C65 c to +150 c voltage on any pin with respect to v ss ......... C1v to +7v d.c. output current ............................................. 5ma lead temperature (soldering, 10 seconds) ............................. 300 c d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) limits symbol parameter min. max. units test conditions i cc v cc supply current (active) 5 ma sck = v cc x 0.1/v cc x 0.9 @ 1mhz, so = open, cs = v ss i sb1 (2) v cc supply current (standby) 1 m a cs = v cc , v in = v ss or v cc , v cc = 3.6v i sb2 v cc supply current (standby) 10 m a cs = v cc , v in = v ss or v cc , v cc = 5v i li input leakage current 10 m av in = v ss to v cc i lo output leakage current C1 10 m av out = v ss to v cc v il (1) input low voltage v cc x 0.7 v cc x 0.3 v v ih (1) input high voltage v cc + 0.5 v v ol1 output low voltage 0.4 v i ol = 1.5ma, v cc = 2.7v v oh1 output high voltage v cc C 0.3 v i oh = C0.4ma, v cc = 2.7v v ol2 output low voltage 0.4 v i ol = 3ma, v cc = 5v v oh2 output high voltage v cc C 0.8 v i oh = C1.6ma, v cc = 5v 6685 pgm t08.4 recommended operating conditions temp min. max. commercial 0 c +70 c extended C20 c +85 c industrial C40 c +85 c 6685 pgm t06.2 supply voltage limits x25f064/032/016/008 1.8v to 3.6v x25f064/032/016/008C5 4.5v to 5.5v 6685 pgm t07.3 power-up timing symbol parameter min. max. units t pur (3) power-up to read operation 1 ms t puw (3) power-up to write operation 5 ms 6685 pgm t09 notes: (1) v il min. and v ih max. are for reference only and are not tested. (2) this parameter is periodically sampled and not 100% tested. (3) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. these parameters are periodically sampled and not 100% tested. capacitance t a = 25 c, f = 1mhz, v cc = 5v. symbol test max. units conditions c out (2) output capacitance (so) 8 pf v out = 0v c in (2) input capacitance (sck, si, cs , wp , hold )6 pf v in = 0v 6685 pgm t10.1
x25f064/032/016/008 9 equivalent a.c. load circuit a.c. test conditions input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 6685 pgm t11 a.c. characteristics (over recommended operating conditions, unless otherwise specified) data input timing symbol parameter min. max. units f sck clock frequency 0 1 mhz t cyc cycle time 1000 ns t lead cs lead time 500 ns t lag cs lag time 500 ns t wh clock high time 400 ns t wl clock low time 400 ns t su data setup time 100 ns t h data hold time 100 ns t ri (4) data in rise time 2 m s t fi (4) data in fall time 2 m s t hd hold setup time 200 ns t cd hold hold time 200 ns t cs cs deselect time 2 m s t pc (5) program cycle time 10 ms 6685 pgm t12.3 data output timing symbol parameter min. max. units f sck clock frequency 0 1 mhz t dis output disable time 500 ns t v output valid from clock low 400 ns t ho output hold time 0 ns t ro (4) output rise time 300 ns t fo (4) output fall time 300 ns t lz (4) hold high to output in low z 100 ns t hz (4) hold low to output in high z 100 ns 6685 pgm t13.2 notes: (4) this parameter is periodically sampled and not 100% tested. (5) t wc is the time from the rising edge of cs after a valid write sequence has been sent to the end of the self-timed internal nonvolatile program cycle. 6685 ill f09.3 output 5v 1.44k w 1.95k w 100pf output 2.7v 1.64k w 4.63k w 100pf
10 x25f064/032/016/008 serial output timing serial input timing sck cs so si msb out msb? out lsb out addr lsb in t cyc t v t ho t wl t wh t dis 6685 ill f10 t lag sck cs si so msb in t su t ri t lag 6685 ill f11 t lead t h lsb in t cs t fi high impedance
x25f064/032/016/008 11 hold timing sck cs si so t hd 6685 ill f12 t lz hold t cd t hz t cd t hd
12 x25f064/032/016/008 packaging information 3926 fhd f01 note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8-lead plastic dual in-line package type p half shoulder width on all end pins optional 0.015 (0.38) max. 0.325 (8.25) 0.300 (7.62)
x25f064/032/016/008 13 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 C 8 x 45 3926 fhd f22.1 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint
14 x25f064/032/016/008 packaging information note: all dimensions in inches (in parentheses in millimeters) 14-lead plastic, tssop package type v see detail a .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 C 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) 3926 fhd f32
x25f064/032/016/008 15 note: all dimensions in inches (in parentheses in millimeters) 20-lead plastic, tssop package type v see detail a .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .252 (6.4) .300 (6.6) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 C 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) 3926 fhd f45 packaging information
16 x25f064/032/016/008 ordering information limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemnification provisions appearing in its terms of sale only. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or fitness for any purpose. xicor, inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no other circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and backup features to prevent such an occurrence. xicor's products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. device x25fxxx p t Cx v cc range blank = 1.8v to 3.6v 5 = 4.5v to 5.5v temperature range blank = commercial = 0 c to +70 c e = extended = C20 c to +85 c i = industrial = C40 c to +85 c package x25f064 X25F032 p = 8-lead plastic dip x25f016 s8 = 8-lead soic x25f008 v = 20-lead tssop p = 8-lead plastic dip s = 8-lead soic v = 14-lead tssop p = 8-lead plastic dip blank = 8-lead soic v = 14/20-lead tssop blank = 1.8v to 3.6v, 0 c to +70 c 5 = 4.5v to 5.5v, 0 c to +70 c i5 = 4.5v to 5.5v, C40 c to +85 c x25fxxx x part mark convention x25f064 X25F032 x25f016 x25f008
x25f064/032/016/008 17 notes
18 x25f064/032/016/008 u.s. sales offices corporate office xicor inc. 1511 buckeye drive milpitas, ca 95035 phone: 408/432-8888 fax: 408/432-0640 e-mail: info@smtpgate.xicor.com northeast region xicor inc. 1344 main street waltham, ma 02154 phone: 617/899-5510 fax: 617/899-6808 e-mail: xicor-ne @smtpgate.xicor.com southeast region xicor inc. 100 e. sybelia ave. suite 355 maitland, fl 32751 phone: 407/740-8282 fax: 407/740-8602 e-mail: xicor-se @smtpgate.xicor.com southwest region xicor inc. 4100 newport place drive suite 710 newport beach, ca 92660 phone: 714/752-8700 fax: 714/752-8634 e-mail: xicor-sw @smtpgate.xicor.com northwest region xicor inc. 2700 augustine drive suite 219 santa clara, ca 95054 phone: 408/292-2011 fax: 408/980-9478 e-mail: xicor-nw @smtpgate.xicor.com mid-atlantic region xicor inc. 50 north street danbury, ct 06810 phone: 203/743-1701 fax: 203/794-9501 e-mail: xicor-ma @smtpgate.xicor.com north central region xicor inc. 810 south bartlett road suite 103 streamwood, il 60107 phone: 708/372-3200 fax: 708/372-3210 e-mail: xicor-nc @smtpgate.xicor.com south central region xicor inc. 11884 greenville ave. suite 102 dallas, tx 75243 phone: 214/669-2022 fax: 214/644-5835 e-mail: xicor-sc @smtpgate.xicor.com international sales offices singapore/malaysia/india xicor inc. 2700 augustine drive suite 219 santa clara, ca 95054 phone: 408/292-2011 fax: 408/980-9478 e-mail: xicor-nw @smtpgate.xicor.com korea xicor korea 27th fl., korea world trade ctr. 159, samsung-dong kangnam ku seoul 135-729 korea phone: (82) 2551.2750 fax: (82) 2551.2710 e-mail: xicor-ka @smtpgate.xicor.com ( ) = country code europe northern europe xicor ltd. grant thornton house witan way witney oxford ox8 6fe uk phone: (44) 1933.700544 fax: (44) 1933.700533 e-mail: xicor-uk @smtpgate.xicor.com central europe xicor gmbh technopark neukeferloh bretonischer ring 15 85630 grasbrunn bei muenchen germany phone: (49) 8946.10080 fax: (49) 8946.05472 e-mail: xicor-gm @smtpgate.xicor.com asia/pacific japan xicor japan k.k. suzuki building, 4th floor 1-6-8 shinjuku, shinjuku-ku tokyo 160, japan phone: (81) 3322.52004 fax: (81) 3322.52319 e-mail: xicor-jp @smtpgate.xicor.com mainland china taiwan/hong kong xicor inc. 4100 newport place drive suite 710 newport beach, ca 92660 phone: 714/752-8700 fax: 714/752-8634 e-mail: xicor-sw @smtpgate.xicor.com xicor, inc., marketing dept. 1511 buckeye drive, milpitas, california 95035-7493 tel 408/432-8888 fax 408/432-0640 rev. 4 3/96 stock# xx-x-xxxx xicor product information is available at: http://www.xicor.com

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